Abstract

The most effective way to reduce phase noise in integrated harmonic oscillators is by rising the active power in the resonator, i.e., scaling down the tank impedance and increasing power consumption. However, in widespread parallel-tank oscillators, a lower bound is readily set by the smallest inductance that can be implemented without incurring into excessive degradation of the quality factor. Emerging multicore oscillators circumvent the issue only partially. In this article, a circuit topology that breaks the phase noise barrier of parallel-tank oscillators is presented. By exploiting the same tank at the series resonance, the remarkably lower tank resistance allows to considerably rise the active power for given voltage swing. As a result, the phase noise is radically reduced without the need for aggressive scaling of the resonator inductor. Two voltage-controlled oscillators (VCOs) in a BiCMOS 55-nm technology exploiting the concept at 10-GHz center frequency are presented. The first design targets an ultra-low phase noise and, with 9% tuning range, demonstrates −138 dBc/Hz at 1-MHz offset with 1.2-V supply and an excellent −190-dBc/Hz figure of merit (FoM). The second design leverages a different implementation of the tank to expand the frequency tuning range and to trade phase noise for power consumption. The tuning range is 16% with a minimum phase noise of −133 dBc/Hz at 1 MHz and −188-dBc/Hz best FoM. To the authors’ knowledge, the presented VCOs demonstrate experimentally the lowest phase noise ever reported with fully integrated oscillators in silicon technology.

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