Abstract

This paper presents an ultra-low phase noise and low-power CMOS LC VCO intended for 5G applications. The proposed design adopts a class-B voltage-biased topology besides incorporating high Q common mode harmonic resonance for ultra-low phase noise performance. Moreover, the design exploits the inherent current reuse mechanism of the complementary cross-coupled configuration to attain a low power consumption level. Furthermore, targeting a sufficient wide tuning range for wideband operation, the designed VCO incorporates both continuous tuning using a low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k_{vco}$</tex> controllable varactor and discrete capacitive tuning through a proposed optimal NMOS-based digitally controlled varactor bank. Designed and simulated in a standard 65 nm RF CMOS technology, the proposed VCO achieves a 16% wide tuning range from 9.2 GHz to 10.8 GHz while consuming a total current of 2.4 mA from a 1 V power supply. Simulated phase noise results showed ultra-low thermal phase noise levels of −124.8 dBc/Hz and −144.8 dBc/Hz at 1 MHz and 10 MHz frequency offsets respectively, while additionally achieving an ultra-low flicker phase noise of −57 dBc/Hz at 1kHz with an outstanding 3.5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{kHz}\ 1/f^{3}$</tex> corner frequency. Accordingly, the designed VCO successfully achieves a superior state-of-the-art peak FoM of 201.7 dBc/Hz and a corresponding 205.7 dBc/Hz FoMT at 1 MHz offsets, which are remarkably the best simulated VCO FoMs of the recently published 10 GHz VCOs.

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