Abstract
In this work, low leakage 0.16 /spl mu/m CMOS devices (T/sub ox/=32 /spl Aring/) with various off-state leakage currents (I/sub off/) were fabricated and studied for low standby power applications. Specifically two different device designs are introduced here. One design code named LP is targeted for worst-case I/sub off/<3 pA//spl mu/m. Another design, code named ULP (ultra low-power), is targeted for even stringent worst-case I/sub off/<0.3 pA//spl mu/m. This work demonstrates n/pMOSFETs with 575/230 and 370/165 /spl mu/A//spl mu/m drive currents @1.8 V for LP and ULP specifications respectively. Cobalt salicide process was also optimized for low junction leakage (<100 pA/cm). The 0.16 /spl mu/m process capability for ultra-low power applications was demonstrated using a CMOS 4 Mbit SRAM with measured minimum standby current <0.2 /spl mu/A at the single power supply voltage V/sub CC/=3 V.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
