Ultralow drive voltage silicon traveling-wave modulator

Tom Baehr-Jones,Michael Hochberg,Matt Streshinsky,Selin Hwee-Gee Teo,Guo-Qiang Lo,Tsung-Yang Liow,Ran Ding,Thierry Pinguet,Nicholas C Harris,Ali Ayazi,Poshen Lee,Yang Liu,Yi Zhang,Andy Eu-Jin Lim

doi:10.1364/oe.20.012014

Abstract

There has been great interest in the silicon platform as a material system for integrated photonics. A key challenge is the development of a low-power, low drive voltage, broadband modulator. Drive voltages at or below 1 Vpp are desirable for compatibility with CMOS processes. Here we demonstrate a CMOS-compatible broadband traveling-wave modulator based on a reverse-biased pn junction. We demonstrate operation with a drive voltage of 0.63 Vpp at 20 Gb/s, a significant improvement in the state of the art, with an RF energy consumption of only 200 fJ/bit.

Highlights

Achieving efficient modulation in the silicon material system has always been one of the key challenges of silicon photonics [1]
A key challenge is the development of a low-power, low drive voltage, broadband modulator
Drive voltages at or below 1 Vpp are desirable for compatibility with CMOS processes

Summary

Introduction

Achieving efficient modulation in the silicon material system has always been one of the key challenges of silicon photonics [1]. One approach taken to lowering the required drive voltage and power consumption has been to use ring resonator geometries [8]. In situations where the temperature of the silicon can change substantially, the realizable energy per bit consumption for resonatorbased modulators will be much higher than the theoretical limits, due to the cost of thermal tuning. It is likely that net power consumption for ring modulator based transmitters will be at least 100-300 fJ/bit Though they have higher power consumption and drive voltage as compared to ring modulators, Mach-Zehnders remain interesting for several reasons. There has been recent progress in lowering the drive voltage in traveling-wave Mach-Zehnder modulators, with on-chip voltages of 2.4 Vpp achieved at speeds up to 30 Gb/s [15]. A drive voltage of 1 Vpp can be utilized in order to minimize device insertion losses

Device geometry and fabrication

Device characterization

Conclusions