Abstract
Ultrafast DC and AC negative bias temperature instability (NBTI) measurements are done in high-k metal gate p-MOSFETs having deeply scaled interlayer. Time evolution of degradation during and after DC and AC stress at different duty cycle and frequency are characterized. Impact of last pulse cycle duration (half or full) and pulse low bias on AC stress are studied. Equivalence of measured data from large and small area devices are shown. Experimental results are qualitatively explained using known NBTI physical mechanism.
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