Abstract
This brief presents an ultra-low voltage split-data-aware 10T and 8T (SDA-10T-8T) embedded static random access memory (SRAM) design for MPEG-4 video processors. Without additional complex peripheral circuits, the proposed design enables a reliable operation at 0.36 V under process variation and aging effect. The experimental results based on 45-nm CMOS technology show that, as compared to conventional SRAM design, our proposed design can achieve a 95% reduction in active power, with no significant degradation in frame quality. In addition, the proposed design suppresses the leakage current effectively, thereby reducing the leakage induced bitline voltage drop rate from 1.54 mV/ns to 0.64 mV/ns at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 0.36 V.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
