Abstract

Carbon Nano Tube Field Effect Transistor is currently considered as promising successor of Metal Oxide Semiconductor Field Effect Transistor. The scaling down of the Metal Oxide Semiconductor device faced serious limits like short channel effect, tunnelling through gate oxide layer, associated leakage currents and power dissipation when its dimension shrink down to 22 nanometer range. Further scaling of Metal Oxide Semiconductor Field Effect Transistor will result in performance degradation. In this study, an ultra low power Single Edge Triggered Delay Flip Flop and shift registers are designed using 10 nanometre Carbon Nano Tube Field Effect Transistor. The Carbon Nano Tube Field Effect Transistor is an efficient device to supplant the current Complementary Metal Oxide Semiconductor technology for its excellent electrical properties. The high electron and hole mobility of semiconductor nano tubes, their compatibility with high k gate dielectrics, enhanced electrostatics, reduced short channel effects and ability to readily form metal ohmic contacts make these miniaturized structures an ideal material for high performance, nanoscale transistors. To evaluate the performance of Ultra low power Single Edge Triggered Delay Flip Flop and shift registers using 10 nanometer Carbon Nano Tube Field Effect Transistor technology, the results are depicted by analyzing average power, delay, power delay product, rise time and fall time using HSPICE at 1GHz operating frequency.

Highlights

  • Even lesser than the average life span of a human and yet it has seen as more than five generations

  • To evaluate the performance of Ultra low power Single Edge Triggered Delay Flip Flop and shift registers using 10 nanometer Carbon Nano Tube Field Effect Transistor technology, the results are depicted by analyzing average power, delay, power delay product, rise time and fall time using HSPICE at 1GHz operating frequency

  • 32 nanometer Carbon nanotube field effect transistors are used as effective replacement of Metal Oxide Semiconductor Field Effect Transistors in digital circuits to overcome the scaling problems

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Summary

INTRODUCTION

Even lesser than the average life span of a human and yet it has seen as more than five generations. Heat is one of the phenomenon packaging challenges in this era, it is one of the main challenges of low power design methodologies and practices Another driver of low power research is the reliability of the integrated circuit. We are moving from laptops to tablets and even smaller computing digital systems With this profound trend continuing and without a match trending in battery life expectancy, the more low power issues will have to be addressed. Wang and Robinson (2010) describes that the current trends will primarily mandate low power design automation on a very large scale to satisfy the trends of power consumption of today’s and future integrated chips. The sources of power consumption in a digital Complementary Metal Oxide Semiconductor circuits are:

Short Circuit Power
Static Power
Capacitance Switching Power
PROPOSED LOW POWER SINGLE EDGE TRIGGERED D-FLIP FLOP
CARBON NANOTUBE FIELD EFFECT TRANSISTOR
Carbon Nanotube Molecular Structure
Ballistic Carbon Nano Tubes Field Effect Transistors
Diameter
SHIFT REGISTERS
TRANSISENT ANALYSIS
PERFORMANCE ANALYSIS
CONCLUSION

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