Ultra‐low‐power adaptable ASK clock and data recovery circuit for wireless implantable systems

Abstract

Amplitude shift keying (ASK) and pulse position modulation (PPM) can be used to provide self-synchronised data and clock for wireless implantable neural recoding systems, and therefore simplifies the circuit architecture. Presented is a novel ultra-low-power clock and data recovery (CDR) circuit based on ASK-PPM. The CDR includes a 1 MHz gain-boosted front-end amplifier with an inductive load for ASK demodulation, and a charge-bump based circuit to extract and recover clock and non-return-to-zero (NRZ) data from the demodulated PPM signal. To increase the input data rate range that is able to be processed by this CDR, the reference voltage required for data recovery is adaptively generated, also from the PPM. The proposed design is fabricated in a standard CMOS 0.25 µm process. It exhibits an input sensitivity of − 13 dBm with 1 MHz input, covers an input data rate range between 19 and 76 kbit/s, and consumes only ∼ 100 µW of power.