Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Abstract

Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy a substantial proportion of chip area and consume significant amounts of power. This paper proposes 18-transistor single-phase clocked (18TSPC), a new topology of fully static contention-free single-phase clocked (SPC) FF with only 18 transistors, the lowest number reported for this type. Implemented in 65-nm CMOS, it achieves 20% cell area reduction compared to the conventional transmission gate FF (TGFF). Simulation results show the proposed 18TSPC is two times more efficient than TGFF in the energy-delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6 V, 25 °C show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.