Abstract
This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage.
Highlights
The complexity of system-on-chip (SoC) is ever growing, while the constraints on power consumption are increasingly tightened
Digital frequency locked loops (FLL) [16] are used in many circuits to generate a stable clock, and are used in dynamic voltage and frequency scaling (DVFS) and adaptive voltage and frequency scaling (AVFS) digital architectures for power management
We chose to work with FLLs because frequency is one of the main parameters we can change to reconfigure a circuit
Summary
The complexity of system-on-chip (SoC) is ever growing, while the constraints on power consumption are increasingly tightened To address this problem, reconfigurable blocks are integrated in SoCs to allow a maximum trade-off between power and performance. It makes access to multiple power islands much easier This approach has proved efficient, and demonstrated that asynchronous design can be adequate to implement communication networks [12]—especially to reduce clocking problems in SoC. There are no clock distribution problems, and power domain crossing is no longer an issue It allows for an easy plug-and-play approach, since the network’s interface can be connected to different types of adaptive blocks, regardless of their architecture or which power domain it will be in.
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