Abstract
Two novel 1-bit Full Adder cells based on Majority Function and the similarity between the minterms of the Cout and Sum functions, are proposed. The cells offer higher speed and less Power-Delay Product (PDP) than the conventional and current implementations of the 1-bit Full Adder cells especially in low voltages. All the input patterns are used for simulation to obtain the delay and the power consumption parameters. Simulations demonstrate improvement in terms of PDP and significant improvement in terms of speed.
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