Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability

Abstract

FinFETs have begun replacing planar CMOS in the post-22 nm era because of their superior short-channel behavior. Though FinFETs will continue to extend Moore's law for the next few technology generations, 3-D vertical integration will enable more-than-Moore density increase by increasing the transistor count that can be accommodated in an IC package. Compared to conventional through-silicon-via (TSV)-based 3-D integration methods, monolithic 3-D integration enables higher density of transistors owing to the much smaller monolithic inter-tier vias (MIVs). In this paper, for the first time, we explore the design possibilities for FinFET-based ultra-high density monolithic 3-D SRAMs. These SRAMs can exploit the height difference between the n- and p-FinFETs placed in two different layers to improve overall SRAM stability. We investigate several 6T and 8T monolithic 3-D FinFET SRAM bitcells and evaluate their dc and transient stability/performance metrics, taking process variations into account. We propose a new 8T 3-D SRAM bitcell that shows a 39% improvement in read stability and 25% improvement in footprint area without affecting writeability, when compared with the conventional 2-D 6T SRAM bitcell.