Abstract
Monolithic three-dimensional (3D) integration provides the most fine-grained integration of transistors. Monolithic inter-tier vias (MIVs) used for inter-tier electrical connections in monolithic 3D integrated circuits (ICs) are as small as local vias, so parasitic resistance and capacitance of an MIV is much smaller than that of a through-silicon via (TSV). In addition, MIVs are much smaller than TSVs, so many MIVs can be inserted into a layout while enabling very high bandwidth between adjacent tiers. Thus, monolithic 3D ICs have been actively researched in the literature recently. In this paper, we proposes a gate composition algorithm to reduce the runtime for routing of monolithic 3D ICs. Simulation results show that the gate composition algorithm reduces the runtime by 11% to 76%.
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