Abstract
Monolithic three-dimensional (3D) integration provides the most fine-grained integration of transistors. Monolithic inter-tier vias (MIVs) used for inter-tier electrical connections in monolithic 3D integrated circuits (ICs) are as small as local vias, so parasitic resistance and capacitance of an MIV is much smaller than that of a through-silicon via (TSV). In addition, MIVs are much smaller than TSVs, so many MIVs can be inserted into a layout while enabling very high bandwidth between adjacent tiers. Thus, monolithic 3D ICs have been actively researched in the literature recently. In this paper, we proposes a gate composition algorithm to reduce the runtime for routing of monolithic 3D ICs. Simulation results show that the gate composition algorithm reduces the runtime by 11% to 76%.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
