Abstract

Monolithic three-dimensional (3D) integrated circuits (ICs) achieve ultra-high density device integration through fine-grained connectivity enabled by monolithic inter-tier vias (MIVs). In this paper, an open source standard cell library for design automation of large-scale transistor-level monolithic 3D ICs is proposed. A 128-point, highly parallelized FFT core with 330K cells is implemented with the proposed library. Power and timing characteristics of monolithic 3D ICs are quantified. The effect of signal integrity and routing congestion on timing characteristics is investigated. The primary clock tree characteristics of monolithic 3D ICs are also discussed. The proposed open source cell library facilitates future research on multiple aspects of monolithic 3D technology.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.