Abstract

This work develops a novel dynamic load modulation Power Amplifier (PA) circuity that can provide an optimum compromise between linearity and efficiency while covering multiple cellular frequency bands. Exploiting monolithic microwave integrated circuits (MMIC) technology, a fully integrated 1W Doherty PA architecture is proposed based on 0.1 μm AlGaAs/InGaAs Depletion-Mode (D-Mode) technology provided by the WIN Semiconductors foundry. The proposed wideband DPA incorporates the harmonic tuning Class-J mode of operation, which aims to engineer the voltage waveform via second harmonic capacitive load termination. Moreover, the applied post-matching technique not only reduces the impedance transformation ratio of the conventional DPA, but also restores its proper load modulation. The simulation results indicate that the monolithic drive load modulation PA at 4 V operation voltage delivers 44% PAE at the maximum output power of 30 dBm at the 1 dB compression point, and 34% power-added efficiency (PAE) at 6 dB power back-off (PBO). A power gain flatness of around 14 ± 0.5 dB was achieved over the frequency band of 23 GHz to 27 GHz. The compact MMIC load modulation technique developed for the 5G mobile handset occupies the die area of 3.2 mm2.

Highlights

  • The multi-standard RF front-end is a continuing research challenge in the B5G/6G legacy, and has focused on high integration level and energy-aware hardware components to support a plethora of smart devices [1]

  • This paper intends to develop an ultra-compact load modulation technical approach for wideband scenarios, targeting next-generation B5G/6G mobile handsets. To achieve this goal, turning to the miniaturized size of the monolithic microwave integrated circuits (MMIC) technology, an asymmetrical Doherty PA (DPA) architecture design is proposed based on the modified Class-J mode of operation, including accurate guidelines to select an optimum impedance at power back-off (PBO)

  • GaAs pseudomorphic highelectron mobility transistor technology facilitates the monolithic integration of low-noise and low-loss passive components covering sub-6 GHz to mm-wave band frequencies

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Summary

Introduction

The multi-standard RF front-end is a continuing research challenge in the B5G/6G legacy, and has focused on high integration level and energy-aware hardware components to support a plethora of smart devices [1]. Most of the broadband DPA approaches have been developed for sub-6 GHz band frequencies based on discrete technologies, while at mm-wave frequencies, the extensive power losses, large parasitic components, current density limitation, and transmission line mutual coupling coefficient present obstacles to the deployment of functional fully integrated IC DPA systems These challenges reduce the effectiveness of the bandwidth extension techniques reported in the literature, and indicate the need for further research efforts. This paper intends to develop an ultra-compact load modulation technical approach for wideband scenarios, targeting next-generation B5G/6G mobile handsets To achieve this goal, turning to the miniaturized size of the MMIC technology, an asymmetrical DPA architecture design is proposed based on the modified Class-J mode of operation, including accurate guidelines to select an optimum impedance at PBO.

Technology Selection
Wideband and Compact Circuit Design Procedure
Stability of the Transistor Cell
Findings
Output Matching Network Design
Full Text
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