Two‐step injection clock generation technique for fractional‐ N MDLL

Abstract

Two-step injection clock generation technique is presented for fine resolution fractional-N multiplying delay-locked loop (MDLL). The coarse DLL generates multiple coarse clock phases, and then fine DLL performs fine phase control for MDLL injection clock. The proposed technique is applied to fractional-N MDLL and efficiently achieves 8b fractional frequency resolution. The MDLL designed in a 0.18 μm CMOS process occupies 0.065 mm2 and generates 10 MHz frequency with 61 μW power consumption.