Abstract
Global buses in deep submicron system-on-chip designs suffer from increasing crosstalk delay as the feature size shrinks. As an technology-independent solution, crosstalk avoidance coding alleviates the problem while requiring less area and power than shielding. Most previously considered crosstalk avoidance codes are one-dimensional, and have limited code rates. In this paper, we propose two-dimensional crosstalk avoidance codes (TDCAC), which achieve higher code rate at the expense of longer latency. Specifically, we investigate the maximum code rate for TDCAC with and without memory.
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