Abstract

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is their overheads in terms of required additional bus lines for representing code words. To solve this problem, in this paper we present a novel CAC that is based on the use of three symbols (three-value) to represent the code words in the bus lines, rather than classical binary CACs based on binary, i.e., 0 and 1 symbols. Our proposed CAC, named summation-based tri-value crosstalk avoidance code (ST-CAC), reduces the worst-case delay in bus lines with respect to binary CACs, and it can efficiently be applied to any arbitrary channel width of lines. The use of three symbols to represent code words in ST-CAC enables to increase the number of code words of a numerical system without increasing the number of required bus lines significantly. The experimental results show that CACs based on the use of three symbols can reduce the number of additional lines compared to binary CACs by 33%. Moreover, we show in the paper, that the delay of wires in the presence our ST-CAC can reduce by 33% with respect to state-of-the-art binary value CACs.

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