Improved crosstalk avoidance codes based on a novel pattern classification

Abstract

The crosstalk delay associated with global on-chip interconnects becomes more serious in deep submicrometer technology, and hence can greatly affect the overall system performance. Based on a delay model proposed by Sotiriadis et al., crosstalk avoidance codes (CACs) have been proposed to alleviate the crosstalk delays by restricting the patterns transmitted on the interconnects. Unfortunately, the effectiveness of these CACs is limited by some drawbacks of the model by Sotiriadis et al. In this paper, we first propose a new classification of transition patterns based on a 5-bit bus, and then provide a method to design CACs with our classification. To illustrate our method, we present a crosstalk avoidance code which achieves a smaller worst-case delay than existing CACs.