Abstract
Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction pMOSFETs with strained SiGe in the source and/or drain have substantially suppressed short-channel effects, including field-induced barrier lowering in the devices with high-k gate dielectrics/spacers. Despite the source-side velocity overshoot, the drive currents in these devices are reduced due to the hetero-barriers in the channel. This drawback can be eliminated by the use of a thin Si or SiGe cap layer. Finally, a novel pMOSFET with a SiGe source/drain and a SiGe quantum well channel is proposed. It has reduced SCE and enhanced drive current.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
