Two methods of realising 10 nm T-gate lithography

Abstract

This paper presents two separate methods for the fabrication of 10 nm footprint T-gates using a two-step gate process. We examine the limits of lithographic and pattern transfer processes using the exposure of ZEP520A resist by electron beam lithography, suitable development processes and subsequent pattern transfer by SF 6 / N 2 reactive ion etching of a silicon nitride layer on III–V substrates. In a second process, the dimensions of a larger initial feature are reduced using the deposition and etching of conformal silicon nitride. Both processes have yielded metallised gates with a footprint as small as 10 nm and are suitable for incorporation into a HEMT process flow.