One platform for all researcher needs
AI-powered academic writing assistant
Your #1 AI companion for literature search
AI tool for graphics, illustrations, and artwork
Unlock unlimited use of all AI tools with the Editage Plus membership.
Explore Editage Plus
Audio Papers
Ask R Discovery
Translation
Auto-sync
Collaboration
https://doi.org/10.1109/54.748804
Copy DOI
Export
Save
Share
Cite Journal: IEEE Design & Test of Computers |  Publication Date: Jan 1, 1999 |
 Citations: 8 |
The authors evaluate two next-generation memory bus architectures approximating SLDRAM and Direct Rambus. Quantifying sources of errors that degrade signal integrity, and considering power dissipation, they show that a fully loaded SLDRAM configuration has a greater timing margin than Direct Rambus.
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
