Abstract
This paper presents the analysis and design of a tun- able CMOS delay gate with improved matching properties as com- pared with the commonly used starved (CSI). The main difference between these structures lies in the location of the current limiting transistor on the inverter's rather than on the side of the power rail. This improves the dynamic per- formance of the proposed output split (OSI) circuit re- ducing the influence of the MOS transistor mismatch on the gen- erated delay time variability. A test chip including two arrays con- sisting of 512 16-stage delay lines employing the CSI and OSI gates hasbeen designed andfabr icated inas tandard 90nmCMOSt ech- nology. The experimental results show that the proposed OSI cir- cuit is about 10-50% more accurate than the conventional current starved inverter with no penalty in terms of the increased area, power consumption or complexity. Applications of the proposed circuit are in the design of time-to-digital converters (TDCs), delay locked loops,readout circuits for particle detection and time-based asynchronous computation systems.
Highlights
T UNABLE CMOS delay gates and delay lines are important functional sub-blocks in a number of applications requiring generation of the controlled delay time intervals such as delay locked loops [1], time-to-digital converters [2], silicon pixel readout circuits for particle detection [3]–[6], asynchronous processor arrays [7], and neuromorphic circuits [8], [9]
We provide a simplified analysis of the switching and discharge phases for both delay gates explaining the influence of the MOS parameter variability on the precision of the generated delays
This paper presented the idea and design of the “output split inverter” delay gate (OSI) exhibiting lower impact of fabrication mismatch on timing parameters than the commonly used current starved inverter (CSI)
Summary
T UNABLE CMOS delay gates and delay lines are important functional sub-blocks in a number of applications requiring generation of the controlled delay time intervals such as delay locked loops [1], time-to-digital converters [2], silicon pixel readout circuits for particle detection [3]–[6], asynchronous processor arrays [7], and neuromorphic circuits [8], [9]. Due to the parameter variability caused by the fabrication process, an array of identically designed delay gates or delay lines will always generate delay time intervals with randomly varying offsets, even under the same bias conditions. Such mismatch of the generated time intervals is usually reported as the dominant factor limiting the precise operation of the entire design. The majority of applications found in literature employ a typical structure of a delay gate based on the current starved inverter (CSI) circuit [Fig. 1(a)] and provide discussions and analyses concerning parameter variability caused by fabrication mismatch [3]–[6].
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