TSV metrology and inspection challenges

Abstract

The interest in 3D packaging and specifically TSV processes has grown significantly in the past few years, with nearly every major chip manufacturer announcing plans to develop and implement this technology. As TSV process flows become stabilized, a number of metrology and inspection issues and opportunities have arisen. Many of these challenges are novel to the industry due to the relatively large size of the vias and new processes such as wafer back-grinding and carrier bonding. This paper summarizes the initial trial process monitoring that has been used during via-first TSV process development at IMEC. This process is designed for SiC (system in chip) applications, using Cu-filled vias measuring 5 um wide by 22 or 50 um deep. While there are a variety of metrology and inspection applications for TSV processing, the main topics covered here are via size measurement, post-grind wafer inspection, and carrier wafer bonding inspection.