Abstract
With the rise of artificial intelligence, automatic driving, 5G, Internet of things and other emerging industries, the demand of 3D integrated packaging technology is increasing strongly to meet the ever-increasing market demands of high performance, small size, high reliability and ultra-low power consumption. This paper presents a new 3D system integrated packaging technology named embedded system in chip (eSinC®) technology. This technology is a combination of TSV technology and eSiFO technology which has been reported in 2016 [1]-[4]. After finishing the standard eSiFO process, backside RDLs and via last TSV process were fabricated by using laser temporary bonding technology. A totally three stacking package including five chips with two layer frontside and backside RDLs was fabricated successfully. Individual package was connected by micro bumps and TSVs. The packaging size is 5×5mm with an overall 0.78mm packaging thickness, while the individual eSinC packaging thickness is 0.28mm. Several key technologies were developed to achieve eSinC package, including high aspect ratio TSVs, wafer thin and handling, low temperature PECVD process, as well as temporary bonding. Good electrical yield was achieved after process optimization.
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