Abstract
Since its introduction in the 1980s, true single-phase clock (TSPC) logic [1] has found widespread use in digital design. Originally proposed as a high-speed topology, the TSPC structure also consumes less power and occupies less area than other methods. In this article, we study the properties of this logic family.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have