Power optimization in TSPC D flip-flop based 4-bit counter

Abstract

In the present communication, the basic D flip flop has been considered with TSPC (True Single Phase Clock) logic for designing a novel 4-bit counter on 45 and 32nm technology. Here, it was with average power of 309 μWatts and 166.8 μWatts, which is very high on the respective technologies. The challenge is to reduce the average power and off state leakage power. To consider the challenge, two different techniques have been considered for power saving as, sleeping transistors and technique, modified TSPC D flip-flop (modified version In comparative study of simulations, it is observed that employing modified version of TSPC D flip-flop shows the most optimum results in terms of propagation delays and average power. Average power has been obtained as 260.3 μWatts which is 15.76% less than base counter on 45nm technology, and 133.2 μWatts which is 20.14 % less on 32nm technology. Moreover, Transistor sizing has also been used for separate analysis in which case the average power consumption has been found most minimum in 6/4 aspect ratio as 196.6 μWatts and 70.31 μWatts in both technologies respectively, among 6/4, 5/3 and 4/2 ratios.