Truly Modular Burst-Mode CDR With Instantaneous Phase Acquisition for Multiaccess Networks

Abstract

We demonstrate a novel 10-Gb/s burst-mode clock and data recovery circuit (BM-CDR) for multiaccess networks. Our design is based on a hybrid topology of a feedback CDR and a feed-forward clock phase aligner utilizing space-sampled clocks. The BM-CDR achieves a bit error rate (BER) while featuring instantaneous (0-bit) phase acquisition for any phase step between successive bursts. We also develop a probabilistic theoretical model for space-sampled BM-CDRs to quantify the BER performance. The theoretical model accounts for the phase step between consecutive packets, packet preamble length, and jitter on the sampling clock.