Abstract
We demonstrate a novel 10-Gb/s burst-mode clock and data recovery circuit (BM-CDR) for multiaccess networks. Our design is based on a hybrid topology of a feedback CDR and a feed-forward clock phase aligner utilizing space-sampled clocks. The BM-CDR achieves a bit error rate (BER) while featuring instantaneous (0-bit) phase acquisition for any phase step between successive bursts. We also develop a probabilistic theoretical model for space-sampled BM-CDRs to quantify the BER performance. The theoretical model accounts for the phase step between consecutive packets, packet preamble length, and jitter on the sampling clock.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.