Triple module redundancy reliability framework design based on heterogeneous multi-core processor

Abstract

Abstract To solve the problem of commercial device with weak anti-SEU ability and traditional radiation hardened device with slow processing speed, this article proposes a novel system-level collaborative triple module redundancy (TMR) design to mitigate single event upset (SEU) on the advanced heterogeneous processor. Based on Xilinx Zynq Ultrascale+ MPSoC, we combine TMR with rolling back, watchdog and scrubbing technique between heterogeneous cores which are Arm Cortex-A53 and Field Programmable Gate Array (FPGA). This combination brings us a promising result of fault identification and correction according to the simulation of the single channel data fault and the double channel data fault. It costs 27%-44% more time to process error and the system has relatively low resource utilization rate and power consumption. Moreover, it can also apply to general heterogeneous quad-core System on Chip (SoC) with FPGA processor’s anti-SEU design and provides some ideas for further study of system level radiation-resistant chips’ design.