Abstract
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability design on FDP2008. Throughput Logic, feedback logic, I/O logic and special feature such as Shift Register LUTs (SRLs) and constant logic are treated differently to effectively mitigate the effects of the SEU faults.
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