Trie Tree Probabilistic Password Cracking Method Based on FPGA

Abstract

Password recovery technology is an important means of Internet electronic evidence. For the low hit rate and slow generation of password cracking, a trie tree probabilistic password cracking method based on FPGA is proposed. Firstly, through the leaked password set, we analyze the user password structure and study the correlation information between characters. Then using the trie tree time-space tradeoff structure features to build password trie tree, which can improve the cracking hit rate. Secondly, the high-speed trie tree password generation algorithm is designed and implemented on FPGA, which speeds up the password generation. Finally, heterogeneous systems are built with CPU and FPGA to achieve a complete application of this method, and some highperformance password recovery algorithms are attacked. The experimental results and analysis show that the password generation speed of this method is about 13 times higher than that of CPU. Compared with the JtR and PCFG attacks, the recovery efficiency and hit rate are improved, and this method has better practical value.