Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State

Abstract

Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines.