Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies

Abstract

With the rapid scaling of CMOS technologies into the nanometer arena, ESD and Latch-up are becoming reliability threats more complex than ever. This paper will systematically address all the challenges related to robust ESD and Latch-up designs as technology scales. The paper will be divided into three distinct parts. In the first part, the intrinsic technology ESD and Latchup scaling characteristics will be reviewed. Particular emphasis will be devoted to nMOS and pMOS scaling, thin-oxide reliability, ESD diodes, metal lines and Latch-up process sensitivity. In the second part, new circuit requirements and their impact on ESD and Latch-up designs will be presented. The challenges associated to the recently introduced power management techniques, ultra low capacitance applications and SoC design will be discussed. Finally, in the third part, unexpected ESD and Latch-up issues such as premature pMOS triggering, unwarranted stress from the HBM tester relay leading to false HBM evaluation, adjacent signal pins interaction and Latch-up will be presented.