Abstract
With the development of process and design technology, the power integrity of low power SOC design meets new problems and challenges. Quantitative analysis is needed to guide the design of power-gating units for low-power SOC design, such as structure selection, the number and size confirmation, and placement optimization. Some new phenomena, such as rush current, rampup time, Power noise coupling and so on, needs to be analyzed and optimized. Static check, dynamic check and powerup analysis are needed to analyze the power performance of low power SOC design. In this paper, ANSYS Redhawk is used to analyze the power integrity of low-power design, and the power performance of low-power SOC design is obtained. Finally, the design of this paper meets the design performance requirements through chip test.
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