Design of the on-chip bus based on Wishbone

Abstract

FPGA and ASIC design based on SoC technology have been widely used in the embedded systems. A flexible interconnection scheme is crucial in SoC design. In this paper, we adopt the Wishbone bus to interconnect a variety of devices due to its open architecture and many a free IP core with a Wishbone interface supplied by OpenCores organization. In general SoC system, a single bus interconnects all devices that are not divided into high-performance unit such as CPU, on-chip ram and low speed devices like uart, gpio and so on. It leads to a big problem: all Wishbone bus cycles run at the speed of the slowest device. We have to add the corresponding logic to regulate the system frequency for some low-speed devices, but it causes a new problem which increases the overall system power consumption. In view of the drawback, based on Wishbone bus, the paper proposes a double bus that makes first level Wishbone bus and the second level bus to interconnect the different devices according to the speed of the devices. Finally, we set up a SoC system to verify the performance of the proposed bus and the result shows that the double bus is feasible in low-power SoC design.