Trap-controlled behavior in ultrathin Lu 2O 3 high-k gate dielectrics

Abstract

Amorphous Lu 2O 3 high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu 2O 3 film has amorphous structure and the interface with Si substrate is free from amorphous SiO 2. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10 −5 A/cm 2 at 1 V accumulation bias was obtained for 4.5 nm thick Lu 2O 3 thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance–voltage ( C– V) and current density–voltage ( J– V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.