Transport mechanisms and charge trapping in thin dielectric/Si nano-crystals structures

Abstract

In this work the transport mechanisms and charge trapping of novel dielectric systems based on semiconductor nano-crystals embedded in a dielectric matrix are studied. In particular, stacked films composed of a thin bottom dielectric (2–4 nm thick SiO2 or Si3N4), with an embedded two-dimensional (2-D) array of Si nano-crystals (obtained by low pressure chemical vapor deposition or by annealing of silicon rich oxide) and a thick top dielectric (8 nm-thick SiO2) are investigated. Gate leakage currents, at medium/high electric fields, are examined at temperatures varying between 77 and 473 K. Charge trapping phenomena, occurring at low electric fields, are studied as a function of the stressing gate voltage and the stressing time. Experimental results are explained by means of an elastic tunneling model, which takes into account the main structural characteristics of the Si-dots (size dispersion, density, spatial distribution) as well as the effect of trapped charges in the silicon nano-crystals.