Abstract
Translinear logic (TLL) is based on a new gate structure which can be realised in a standard bipolar technology. Initial results from a conservative (10 μm) process indicate a packing density of 40 gates/mm2 and a minimum gate delay of 3 ns. Compared to integrated Schottky logic (ISL) made with the same process, TLL has a similar packing density but is four times faster.
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