Performance, temperature behavior, and first-order modeling of ISL

Abstract

The minimum propagation delay time of integrated Schottky logic (ISL) made in a standard LS process is determined by saturation of the vertical p-n-p clamp transistor. A performance improvement is obtained by increasing the dope of the substrate to prevent this saturation effect. When using 5 /spl mu/m minimum dimensions the minimum propagation delay is then well below 3 ns over the full temperature range from -55 up to 150/spl deg/C chip temperature. It is shown that a vertical p-n-p clamp transistor is essential to obtain a high speed when relaxed design rules are used. Furthermore, it is shown that ISL can be modeled in a relatively simple manner with one n-p-n transistor and one or two p-n-p transistors, depending on the resistivity of the substrate.