Abstract
This paper presents a BIST design suitable for detecting multiple stuck-open faults in two-level CMOS single complex cells. The test pattern generator (TPG) generates a sequence of length 2n.2/sup n/ that includes all n.2/sup n/ single-input-change (SIC) ordered test pairs for an n-input circuit under test (CUT). The signature analyzer (SA) counts the number of alternate transitions at the output. Design of the corresponding TPG and SA is straightforward.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
