Abstract
Transient voltage overshoots of a high voltage (20 V) ESD clamp based on bipolar transistors in a smart power technology are studied using different TLP pulse conditions (rise time, voltage amplitude). The physical mechanisms involved during the ESD clamp turn-on are thoroughly analyzed by the mean of TCAD simulations, allowing the definition of a set of design guidelines for the overshoot reduction.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
