Abstract
Under a given set of boundary conditions, thermal performance of an electronic system is generally evaluated based on its steady state response. It is a conventional practice that actual time dependent power cycles and thermal boundary conditions are time-averaged to estimate the steady state characteristics. This approach may produce accurate results provided that the time dependency of the power cycles and/or thermal boundary conditions is small. In general, time-dependent thermal analyses with actual time-dependent boundary conditions and power cycles should be performed in order to determine the steady state behavior. Whether an experimental or numerical approach is taken, accurate prediction of transient thermal behavior of complex electronic systems is time consuming. While being less overwhelming compared to the actual laboratory experiments, fully time dependent Computational Fluid Dynamics (CFD) analysis still requires large amount of CPU time. In order to prevail over this large computational cost, a number of approximate models were developed, such as Resistor-Capacitor (R-C) thermal network approaches which have produced reasonably accurate results, and therefore have been popular in determining system transient response. It is worth noting that these approaches require some rigorous curve-fitting effort followed by an optimization process and are applicable to relatively simple systems. The present study uses state-space model to determine transient and steady state thermal behavior of complex systems as accurately as possible without compromising the speed. The aforementioned technique is applied to a “Small Outline Integrated Circuit” (SOIC) package placed on a printed circuit board (PCB) and the results are compared to those from the fully transient CFD model computations. With a dramatic reduction in the overall CPU times, the temperature histories obtained from the state-space approach agree well with the transient CFD simulations. Furthermore, an optimization scheme is defined so that the maximum temperature on the package is kept under a specified value by changing the power cycles on individual die elements which may be of great benefit to the chip designers especially at the early stages of design.
Published Version
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