Transconductor Linearization Based On Adaptive Biasing of Source-Degenerative MOS Transistors

Abstract

This paper presents a novel linearization technique for a transconductance amplifier. Resistive source degeneration as commonly used technique for linearization of the differential pairs suffers from input-dependent variations in degeneration resistance when passive resistor is substituted by active counterpart to achieve lower area usage and tuning ability. The proposed technique is based on using an auxiliary circuit to adaptively bias degenerative transistors to reduce the resistance nonlinearity caused by applying input voltage. The proposed transconductor employs $$\pm $$±0.9 V power supply and totally consumes 139.2 $$\upmu $$μW in which the portion of auxiliary circuit including tuning circuit is only 17 %. Simulation results in 0.18 $$\upmu $$μm TSMC technology by Hspice simulator indicate 13.2 dB reduction in the third-order harmonic distortion of proposed transconductor's output current compared with conventional case, when a 1.2 Vp---p input voltage is applied at 10 MHz frequency. The corner case and Monte Carlo simulations verify the robustness of the proposed technique against the fabrication process errors.