Abstract
The trading of speed for low power consumption in CMOS VLSI by using the supply voltage and the threshold voltage as variables was investigated. It is shown that it is desirable to minimize the supply voltage for minimizing the power consumption. The lower bound of the supply voltage and the possible decrease in power consumption without speed loss were investigated under different circuit constraints, and the consequences for circuit performance were calculated. Results show, for example, that power reductions of about 40 times can be obtained without speed loss by using supply voltages down to about 0.48 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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