Trade-offs in the integration of high performance devices with trench capacitor DRAM

Abstract

This paper demonstrates it is possible to enhance the device performance of a standard DRAM process by 35% with only a moderate reduction in retention time. We have also merged high-performance logic devices and working DRAM at the cost of an appreciable degradation in retention behavior and a slightly larger cell. The device performance is 1.82/spl times/ the base process. This demonstrates that embedding DRAM in a high-performance technology is feasible although the optimum trade-off between performance, density, retention time, cost, and power depends on the application.