Trace line failure analysis and characterization of the panel base package (PBP™) technology with fan-out capability

Abstract

The wafer level package (WLP) is a cost-effective solution for the electronic package, and has been increasingly applied during recent years. In this study, a new packaging technology developed based on the concepts of the WLP, the panel base package (PBP) technology, is proposed in order to further obtain the capability of signals fan-out for the fine-pitched integrated circuit (IC). In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface, and the pitch of the chip side is fanned-out. The design concept and the manufacturing process of the PBP would first be described in this study. The three-dimensional finite element (FE) model is established based on the real testing sample, and the thermo-mechanical behavior of the PBP is simulated. It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer (SBL). However, the accumulated stress/strain from the coefficient of thermal expansion (CTE) mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid the stress concentration effect.