Failure Mode and Thermal Performance Analysis of Stacked Panel Level Package (PLP)

Abstract

In this paper, a new packaging technology, chip-on-metal (COM) panel level package (PLP), with stacking and fan-out capabilities is proposed. Moreover, the concept of the COM PLP and the process of its fabrication are described. During the manufacturing process, the trench around the chip is filled with the filler polymer material. Therefore, the solder bumps could be located on both the filler polymer and the chip surfaces by the redistribution lines, and the pitch of the chip side is fanned-out. In our previous research, it was shown that the physical behavior of the COM PLP is different from that of the conventional wafer level package (WLP). To assess the thermal performance and thermo-mechanical characteristic of the proposed PLP, the finite element analysis (FEA) in board level is carried out. The junction temperature and thermal resistance of the COM PLP and the stacked PLP are discussed to study the thermal performance. At the same time, the mean cycle to failure of the solder joints is predicted, and the result shows that the reliability of solder joints can be highly improved by the proposed packaging technology. However, the new failure mode may occur at the metallic traces so the reliability assessment of the signal trace is also investigated. In addition, the parametric analysis of the COM PLP is studied to enhance the thermal performance and reliability characteristic. Thus, the PLP technology will have high potential for various applications in the near future.