Abstract
Wireless communication above 100 GHz offers the potential for massive data rates and has attracted considerable attention for Beyond 5G and 6G systems. A key challenge in the receiver design in these bands is power consumption, particularly for mobile and portable devices. This paper provides a general methodology for understanding the trade-offs of power consumption and end-to-end performance of a large class of potential receivers for these frequencies. The framework is applied to the design of a fully digital 140 GHz receiver with a 2 GHz sample rate, targeted for likely 6G cellular applications. Design options are developed for key RF components including the low noise amplifier (LNA), mixer, local oscillator (LO) and analog-digital converter (ADC) in 90 nm SiGe BiCMOS. The proposed framework, combined with detailed circuit and system simulations, is then used to select among the design options for the overall optimal end-to-end performance and power tradeoff. The analysis reveals critical design choices and bottlenecks. It is shown that optimizing these critical components can enable a dramatic 70 to 80% power reduction relative to a standard baseline design enabling fully-digital 140 GHz receivers with RF power consumption less than 2 W.
Highlights
There has been growing interest in communication systems above 100 GHz where vast swaths of largely unused spectrum offer the potential for links with massive data rates and ultra low latencies [1]
Effective Noise Figure and Saturation SNR: We argue that, for a large class of practical systems, the input-output SNR relation can be described by two VOLUME 9, 2021 key parameters: (i) An effective noise figure that applies in a low input signal regime, and (ii) a saturation SNR that applies in a high input SNR regime
Consistent with [9], our analysis reveals that once low resolution analog-digital converter (ADC) are used, the mixer and local oscillator (LO) distribution are the dominant components in the power consumption
Summary
There has been growing interest in communication systems above 100 GHz where vast swaths of largely unused spectrum offer the potential for links with massive data rates and ultra low latencies [1]. The broad purpose of this paper is to provide a methodology to understand the performance and power consumption tradeoffs in the receiver radio frequency front-end (RFFE) and develop new designs to better optimize that tradeoff. To this end, we develop an analytic framework for characterizing the end-to-end performance of a large class of potential receiver designs. To consider practical features of radio architecture and packaging for large arrays, we consider a super-heterodyne structure, as opposed to a direct conversion because it separates the front-end and baseband circuit blocks to support the fine pitch in frequency bands above 100 GHz. it will allow us to optimize the image rejection and the dynamic range of the system [24]. The analysis can be applied to phased array and direct conversion architectures as well
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