An 8-bit 1 Gsps CMOS pipeline ADC

Abstract

An 8-bit 1Gsamples/s CMOS pipeline ADC(analog to digital converter) is designed with an open loop circuit design technique. To achieve the 1 GHz sampling rate, an interleaving technique is used. To get low power consumption and small die area, common blocks, such as, a reference string, bias blocks, interpolation amplifiers and pre-amplifiers in comparator are shared. At the 1 GHz sampling rate, simulation results show that the power consumption is 400 mW including digital logic with a power supply of 1.8 V and the SNDR of 45 dB with an input frequency of 207 MHz. The proposed ADC was designed with 0.18 /spl mu/m 6-Metal 1-Poly CMOS process and occupies an die area of 800 /spl mu/m /spl times/ 950 /spl mu/m. The prototype device is now under fabrication.