Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques

Abstract

Increasing the fault and test coverage is an important goal in the DFT strategies of semiconductor companies. In particular, the growing distribution in the automotive market leads to strict test requirements and high fault coverage demands. A wide-spread method to increase the fault coverage is to insert controllability and observability test points in order to ease fault excitation and detection. Since test points cause hardware overhead, it is important to restrict their number to a minimum to prevent high costs. The paper targets the identification of effective test points in order to make untestable faults testable. Optimization-SAT-based ATPG techniques are used to calculate a minimum set of effective test points, which is able to make all previously undetectable faults of a fault set $F$ detectable. Additionally, untestable fault ordering heuristics are introduced to reduce the number of needed test points. Experimental results on benchmark circuits show that the proposed method is able to generate a small set of test points, which is able to provide 100% fault coverage for stuck-at faults.